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2, 4 meg x 64 sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm02.p65 C rev. 6/98 ? 1998, micron technology, inc. 1 2, 4 meg x 64 sdram dimms obsolete pin symbol pin symbol pin symbol pin symbol 1v ss 43 v ss 85 v ss 127 v ss 2 dq0 44 dnu 86 dq32 128 cke0 3 dq1 45 s2# 87 dq33 129 s3#* 4 dq2 46 dqmb2 88 dq34 130 dqmb6 5 dq3 47 dqmb3 89 dq35 131 dqmb7 6v dd 48 dnu 90 v dd 132 rfu 7 dq4 49 v dd 91 dq36 133 v dd 8 dq5 50 nc 92 dq37 134 nc 9 dq6 51 nc 93 dq38 135 nc 10 dq7 52 nc 94 dq39 136 nc 11 dq8 53 nc 95 dq40 137 nc 12 v ss 54 v ss 96 v ss 138 v ss 13 dq9 55 dq16 97 dq41 139 dq48 14 dq10 56 dq17 98 dq42 140 dq49 15 dq11 57 dq18 99 dq43 141 dq50 16 dq12 58 dq19 100 dq44 142 dq51 17 dq13 59 v dd 101 dq45 143 v dd 18 v dd 60 dq20 102 v dd 144 dq52 19 dq14 61 nc 103 dq46 145 nc 20 dq15 62 nc 104 dq47 146 nc 21 nc 63 cke1* 105 nc 147 nc 22 nc 64 v ss 106 nc 148 v ss 23 v ss 65 dq21 107 v ss 149 dq53 24 nc 66 dq22 108 nc 150 dq54 25 nc 67 dq23 109 nc 151 dq55 26 v dd 68 v ss 110 v dd 152 v ss 27 we# 69 dq24 111 cas# 153 dq56 28 dqmb0 70 dq25 112 dqmb4 154 dq57 29 dqmb1 71 dq26 113 dqmb5 155 dq58 30 s0# 72 dq27 114 s1#* 156 dq59 31 dnu 73 v dd 115 ras# 157 v dd 32 v ss 74 dq28 116 v ss 158 dq60 33 a0 75 dq29 117 a1 159 dq61 34 a2 76 dq30 118 a3 160 dq62 35 a4 77 dq31 119 a5 161 dq63 36 a6 78 v ss 120 a7 162 v ss 37 a8 79 ck2 121 a9 163 ck3 38 a10 80 nc 122 ba0 164 nc 39 rfu 81 nc/wp** 123 rfu 165 sa0 40 v dd 82 sda 124 v dd 166 sa1 41 v dd 83 scl 125 ck1 167 sa2 42 ck0 84 v dd 126 rfu 168 v dd *32mb version only **-10b only pin assignment (front view) synchronous dram module mt8lsdt264a, MT16LSDT464A for the latest data sheet revisions, please refer to the micron web site: www.micron.com/mti/msp/html/datasheet.html features ? pc100-compliant; includes concurrent auto precharge ? jedec-standard 168-pin, dual in-line memory module (dimm) ? nonbuffered ? 16mb (2 meg x 64) and 32mb (4 meg x 64) ? single +3.3v 0.3v power supply ? fully synchronous; all signals registered on positive edge of system clock ? internal pipelined operation; column address can be changed every clock cycle ? internal banks for hiding row access/precharge ? programmable burst lengths: 1, 2, 4, 8 or full page ? auto precharge and auto refresh modes ? self refresh mode ? 64ms, 4,096-cycle refresh ? lvttl-compatible inputs and outputs ? serial presence-detect (spd) options marking ? package 168-pin dimm (gold) g ? frequency/cas latency 100 mhz/cl = 3 (8ns sdrams) -10b 66 mhz/cl = 2 (10ns sdrams) -662 ? component revision designator alpha character factory defined ? printed circuit board revision designator numeric character factory defined 168-pin dimm key sdram component timing parameters module speed cas access setup hold marking grade latency time time time -10b -8b 3 6ns 2ns 1ns -662 -10 2 9ns 3ns 1ns
2, 4 meg x 64 sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm02.p65 C rev. 6/98 ? 1998, micron technology, inc. 2 2, 4 meg x 64 sdram dimms obsolete part numbers part number configuration system bus speed mt8lsdt264ag-10b_ 2 meg x 64 100 mhz mt8lsdt264ag-662_ 2 meg x 64 66 mhz MT16LSDT464Ag-10b_ 4 meg x 64 100 mhz MT16LSDT464Ag-662_ 4 meg x 64 66 mhz note : all part numbers end with a two-place code (not shown), designating component and pcb revisions. consult factory for current revision codes. example: mt8lsdt264ag-10b d2. general description the mt8lsdt264a and MT16LSDT464A are high-speed cmos, dynamic random-access, 16mb and 32mb memo- ries organized in a x64 configuration. these modules use sdrams that are internally configured as dual memory arrays with a synchronous interface (all signals are regis- tered on the positive edge of the clock signals ck0-ck3). read and write accesses to the sdram module are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the registration of an ac- tive command, which is then followed by a read or write command. the address bits registered coincident with the active command are used to select the bank and row to be accessed (ba0 selects the bank; a0-a10 select the row). the address bits registered coincident with the read or write command are used to select the starting column location for the burst access. the modules provide for programmable read or write burst lengths of 1, 2, 4 or 8 locations, or full page, with a burst terminate option. an auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. the modules use an internal pipelined architecture to achieve high-speed operation. this architecture is compat- ible with the 2 n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a high-speed, fully random access. precharging one bank while accessing the alternate bank will hide the precharge cycles and provide seamless, high-speed, random-access operation. the modules are designed to operate in 3.3v, low-power memory systems. an auto refresh mode is provided, along with a power-saving, power-down mode. all inputs and outputs are lvttl-compatible. sdram modules offer substantial advances in dram operating performance, including the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave be- tween internal banks in order to hide precharge time and the capability to randomly change column addresses on each clock cycle during a burst access. for more information regarding the sdram operation, refer to the 16mb: x4, x8 sdram data sheet. serial presence-detect operation this module incorporates serial presence-detect (spd). the spd function is implemented using a 2,048-bit eeprom. this nonvolatile storage device contains 256 bytes. the first 128 bytes can be programmed by micron to identify the module type and various sdram organizations and tim- ing parameters. the remaining 128 bytes of storage are available for use by the customer. system read/write operations between the master (system logic) and the slave eeprom device (dimm) occur via a standard iic bus using the dimms scl (clock) and sda (data) signals, together with sa(2:0), which provide eight unique dimm/eeprom addresses.
2, 4 meg x 64 sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm02.p65 C rev. 6/98 ? 1998, micron technology, inc. 3 2, 4 meg x 64 sdram dimms obsolete spd clock and data conventions data states on the sda line can change only during scl low. sda state changes during scl high are reserved for indicating start and stop conditions (figures 1 and 2). spd start condition all commands are preceded by the start condition, which is a high-to-low transition of sda when scl is high. the spd device continuously monitors the sda and scl lines for the start condition and will not respond to any command until this condition has been met. spd stop condition all communications are terminated by a stop condition, which is a low-to-high transition of sda when scl is high. the stop condition is also used to place the spd device into standby power mode. spd acknowledge acknowledge is a software convention used to indicate successful data transfers. the transmitting device, either master or slave, will release the bus after transmitting eight bits. during the ninth clock cycle, the receiver will pull the sda line low to acknowledge that it received the eight bits of data (figure 3). the spd device will always respond with an acknowl- edge after recognition of a start condition and its slave address. if both the device and a write operation have been selected, the spd device will respond with an ac- knowledge after the receipt of each subsequent eight-bit word. in the read mode the spd device will transmit eight bits of data, release the sda line and monitor the line for an acknowledge. if an acknowledge is detected and no stop condition is generated by the master, the slave will continue to transmit data. if an acknowledge is not detected, the slave will terminate further data transmissions and await the stop condition to return to standby power mode. scl sda data stable data stable data change figure 1 data validity scl sda start bit stop bit figure 2 definition of start and stop scl from master data output from transmitter data output from receiver 9 8 acknowledge figure 3 acknowledge response from receiver
2, 4 meg x 64 sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm02.p65 C rev. 6/98 ? 1998, micron technology, inc. 4 2, 4 meg x 64 sdram dimms obsolete functional block diagram mt8lsdt264a (16mb) dqm cs# u7 note : all resistor values are 10 ohms. u0-u7 = mt48lc2m8a1tg sdrams a0 sa0 spd sda a1 sa1 a2 sa2 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 dqmb7 dqm cs# u6 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 dqmb6 dqm cs# u5 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 dqmb5 dqm cs# u4 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 dqmb4 dqm cs# u3 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 dqmb3 dqm cs# u2 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 dqmb2 dqm cs# u1 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dqmb1 dqm cs# u0 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dqmb0 s2# s0# ras# cas# cke0 we# ras#: sdrams u0-u7 cas#: sdrams u0-u7 cke0: sdrams u0-u7 we#: sdrams u0-u7 a0-a10: sdrams u0-u7 ba: sdrams u0-u7 a0-a10 ba0 v dd v ss sdrams u0-u7 sdrams u0-u7 10pf ck2, ck3 u0 u4 u1 u5 ck0 u2 u6 u3 u7 ck1 10pf ck1, ck3 sdram sdram sdram sdram ck0 sdram sdram sdram sdram ck2 3.3pf 3.3pf 66 mhz versions 100 mhz versions scl wp 47k
2, 4 meg x 64 sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm02.p65 C rev. 6/98 ? 1998, micron technology, inc. 5 2, 4 meg x 64 sdram dimms obsolete functional block diagram MT16LSDT464A (32mb) dqm cs# u7 note : all resistor values are 10 ohms u0-u15 = mt48lc2m8a1tg sdrams unless otherwise specified. a0 sa0 spd sda a1 sa1 a2 sa2 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 dqmb7 dqm cs# u6 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 dqmb6 dqm cs# u5 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 dqmb5 dqm cs# u4 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 dqmb4 dqm cs# u3 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 dqmb3 dqm cs# u2 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 dqmb2 dqm cs# u1 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dqmb1 dqm cs# u0 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dqmb0 s2# s0# cke1 cke0 cas# ras# we# cke: sdrams u8-u15 cke: sdrams u0-u7 cas#: sdrams u0-u15 ras#: sdrams u0-u15 we#: sdrams u0-u15 a0-a10: sdrams u0-u15 ba: sdrams u0-u15 a0-a10 ba0 v dd v ss sdrams u0-u15 sdrams u0-u15 dqm cs# u15 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dqm cs# u14 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dqm cs# u13 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dqm cs# u12 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 s1# dqm cs# u11 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dqm cs# u10 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dqm cs# u9 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dqm cs# u8 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 s3# v dd 10k u0 u4 u8 u12 ck0 u1 u5 u9 u13 ck1 u10 u14 u2 u6 ck2 u3 u7 u11 u15 ck3 66 mhz versions sdram sdram sdram sdram ck0 sdram sdram sdram sdram ck1 3.3pf 3.3pf 100 mhz versions sdram sdram sdram sdram ck2 3.3pf sdram sdram sdram sdram ck3 3.3pf scl wp 47k
2, 4 meg x 64 sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm02.p65 C rev. 6/98 ? 1998, micron technology, inc. 6 2, 4 meg x 64 sdram dimms obsolete pin descriptions pin numbers symbol type description 115, 111, 27 ras#, cas#, input command inputs: ras#, cas# and we# (along with we# s0#-s3#) define the command being entered. 42, 125, 79, 163 ck0-ck3 input clock: ck0-ck3 are driven by the system clock. all sdram input signals are sampled on the positive edge of ck. ck also increments the internal burst counter and controls the output registers. 128, 63 cke0, cke1 input clock enable: cke0-cke1 activate (high) and deactivate (low) the ck0-ck3 signals. deactivating the clock provides power-down and self refresh operation (all banks idle) or clock suspend operation (burst access in progress). cke0-cke1 are synchronous except after the device enters power-down and self refresh modes, where cke0-cke1 become asynchronous until after exiting the same mode. the input buffers, including ck0- ck3, are disabled during power-down and self refresh modes, providing low standby power. 30, 114, 45, 129 s0#-s3# input chip select: s0#-s3# enable (registered low) and disable (registered high) the command decoder. all commands are masked when s0#-s3# are registered high. s0#-s3# are considered part of the command code. 28-29, 46-47, dqmb0-dqmb7 input input/output mask: dqmb is an input mask signal for 112-113, 130-131 write accesses and an output enable signal for read accesses. input data is masked when dqmb is sampled high during a write cycle. the output buffers are placed in a high-z state (two-clock latency) when dqmb is sampled high during a read cycle. 122 ba0 input bank address: ba0 defines to which bank the active, read, write or precharge command is being applied. ba0 is also used to program the 12th bit of the mode register. 33-38, 117-121 a0-a10 input address inputs: a0-a10 are sampled during the active command (row-address a0-a10) and read/write command (column-address a0-a8, with a10 defining auto precharge) to select one location out of the memory array in the respective bank. a10 is sampled during a precharge command to determine if both banks are to be precharged (a10 high). the address inputs also provide the op-code during a load mode register command. 2-5, 7-11, 13-17, 19-20, dq0-dq63 input/ data i/o: data bus. 55-58, 60, 65-67, 69-72, output 74-77, 86-89, 91-95, 97-101, 103, 104, 139-142, 144, 149-151, 153-156, 158-161
2, 4 meg x 64 sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm02.p65 C rev. 6/98 ? 1998, micron technology, inc. 7 2, 4 meg x 64 sdram dimms obsolete 6, 18, 26, 40, 41, 49, 59, v dd supply power supply: +3.3v 0.3v. 73, 84, 90, 102, 110, 124, 133, 143, 157, 168 1, 12, 23, 32, 43, 54, 64, v ss supply ground. 68, 78, 85, 96, 107, 116, 127, 138, 148, 152, 162 81 wp input write protect: serial presence-detect hardware write protect. applies to -10b version only. 82 sda input/output serial presence-detect data: sda is a bidirectional pin used to transfer addresses and data into and out of the presence-detect portion of the module. 83 scl input serial clock for presence-detect: scl is used to synchro- nize the presence-detect data transfer to and from the module. 165-167 sa0-sa2 input presence-detect address inputs: these pins are used to configure the presence-detect device. 39, 123, 126, 132 rfu C reserved for future use: these pins should be left unconnected. 31, 44, 48 dnu C do not use: these pins are not connected on these modules but are assigned pins on the compatible dram version. pin descriptions (continued) pin numbers symbol type description
2, 4 meg x 64 sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm02.p65 C rev. 6/98 ? 1998, micron technology, inc. 8 2, 4 meg x 64 sdram dimms obsolete note: 1. 1/0: serial data, driven to high/driven to low. serial presence-detect matrix byte description entry (version) symbol bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 hex 0 number of bytes used by micron 128 10000000 80 1 total number of spd memory bytes 256 00001000 08 2 memory type sdram 00000100 04 3 number of row addresses 11 00001011 0b 4 number of column addresses 9 00001001 09 5 number of banks 1 (16mb) 00000001 01 2 (32mb) 00000010 02 6 module data width 64 01000000 40 7 module data width (continued) 0 00000000 00 8 module voltage interface levels lvttl 00000001 01 9 sdram cycle time 8 (-10b) t ck 10000000 80 (cas latency = 3) 10 (-662) 10100000 a0 10 sdram access from clock 6 (-10b) t ac 01100000 60 (cas latency = 3) 7.5 (-662) 01110101 75 11 module configuration type nonparity 00000000 00 12 refresh rate/type 15.6 m s/self 10000000 80 13 sdram width (primary sdram) 8 00001000 08 14 error-checking sdram data width none 00000000 00 15 minimum clock delay from back-to-back 1 t ccd 00000001 01 random column addresses 16 burst lengths supported 1, 2, 4, 8 page 10001111 8f 17 number of banks on sdram device 2 00000010 02 18 cas latencies supported 1, 2, 3 00000111 07 19 cs latency 0 00000001 01 20 we latency 0 00000001 01 21 sdram module attributes nonbuffered 00000000 00 22 sdram device attributes: general 0e 00001110 0e 23 sdram cycle time 12 (-10b) t ck 11000000 c0 (cas latency = 2) 15 (-662) 11110000 f0 24 sdram access from clk 9 t ac 10010000 90 (cas latency = 2) 25 sdram cycle time 30 t ck 01111000 78 (cas latency = 1) 26 sdram access from clk 27 t ac 01101100 6c (cas latency = 1) 27 minimum row precharge time 24 (-10b) t rp 00011000 18 30 (-662) 00011110 1e 28 minimum row active to row active 20 t rrd00010100 14 29 minimum ras# to cas# delay 20 (-10b) t rcd 00010100 14 30 (-662) 00011110 1e 30 minimum ras# pulse width 50 (-10b) t ras 00110010 32 60 (-662) 00111110 3c 31 module bank density 16mb 00000100 04 32 command and address setup time 2 (-10b) t as, t cms00100000 20 0 (-662) 00000000 00
2, 4 meg x 64 sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm02.p65 C rev. 6/98 ? 1998, micron technology, inc. 9 2, 4 meg x 64 sdram dimms obsolete serial presence-detect matrix (continued) byte description entry (version) symbol bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 hex 33 command and address hold time 1 (-10b) t ah, t cmh00010000 10 0 (-662) 00000000 00 34 data signal input setup time 2 (-10b) t ds 00100000 20 0 (-662) 00000000 00 35 data signal input hold time 1 (-10b) t dh 00010000 10 0 (-662) 00000000 00 36-61 reserved 00000000 00 62 spd revision rev. 1.2 (-10b) 00010010 12 rev. 1.0 (-662) 00000001 01 63 checksum for bytes 0-62 16mb (-10b) 00001111 0f 16mb (-662) 00011000 1d 32mb (-10b) 00010000 10 32mb (-662) 00011001 1e 64 manufacturers jedec id code micron 00101100 2c 65-71 manufacturers jedec id code (cont.) 11111111 ff 72 manufacturing location 00000001 01 00000010 02 00000011 03 00000100 04 00000101 05 00000110 06 73-90 module part number (ascii) xxxxxxxx xx 91 pcb identification code 1 00000001 01 2 00000010 02 3 00000011 03 4 00000100 04 92 identification code (cont.) 0 00000000 00 93 year of manufacture in bcd xxxxxxxx xx 94 week of manufacture in bcd xxxxxxxx xx 95-98 module serial number xxxxxxxx xx 99-125 manufacturer-specific data (rsvd) CCCCCCCC C 126 system frequency 100 mhz (-10b) 01100100 64 66 mhz (-662) 01100110 66 127 sdram component & clock detail 16mb (-10b) 10101101ad 32mb (-10b) 11111101 fd (-662) 00000110 06 note: 1. 1/0: serial data, driven to high/driven to low. 2. x = variable data.
2, 4 meg x 64 sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm02.p65 C rev. 6/98 ? 1998, micron technology, inc. 10 2, 4 meg x 64 sdram dimms obsolete commands truth table 1 provides a general reference of available commands. for a more detailed description of commands and operations, refer to the 16mb: x4, x8 sdram data sheet. note: 1. cke is high for all commands shown except self refresh. 2. a0-a10 and ba0 define the op-code written to the mode register. 3. a0-a10 provide row address, and ba0 determines which bank is made active (ba0 low = bank 0; ba0 high = bank 1). 4. a0-a8 provide column address; a10 high enables the auto precharge feature (nonpersistent), while a10 low disables the auto precharge feature; ba0 determines which bank is being read from or written to (ba0 low = bank 0; ba0 high = bank 1). 5. a10 low: ba0 determines which bank is being precharged (ba0 low = bank 0; ba0 high = bank 1). a10 high: both banks are precharged and ba0 is dont care. 6. this command is auto refresh if cke is high, self refresh if cke is low. 7. internal refresh counter controls row addressing; all inputs and i/os are dont care except for cke. 8. activates or deactivates the dqs during writes (zero-clock delay) and reads (two-clock delay). truth table 1 C commands and dqmb operation (notes: 1) name (function) cs# ras# cas# we# dqmb addr dqs notes command inhibit (nop) h xxxx x x no operation (nop) l h h h x x x active (select bank and activate row) l l h h x bank/row x 3 read (select bank and column, and start read burst) l h l h x bank/col x 4 write (select bank and column, and start write burst) l h l l x bank/col valid 4 burst terminate l h h l x x active precharge (deactivate row in bank or banks) l l h l x code x 5 auto refresh or l l l h x x x 6, 7 self refresh (enter self refresh mode) load mode register l l l l x op-code x 2 write enable/output enable CCCCl C active 8 write inhibit/output high-z CCCCh C high-z 8
2, 4 meg x 64 sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm02.p65 C rev. 6/98 ? 1998, micron technology, inc. 11 2, 4 meg x 64 sdram dimms obsolete note: 1. for a burst length of two, a1-a8 select the block-of- two burst; a0 selects the starting column within the block. 2. for a burst length of four, a2-a8 select the block-of- four burst; a0-a1 select the starting column within the block. 3. for a burst length of eight, a3-a8 select the block-of- eight burst; a0-a2 select the starting column within the block. 4. for a full-page burst, the full row is selected, and a0-a8 select the starting column. 5. whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 6. for a burst length of one, a0-a8 select the unique column to be accessed, and mode register bit m3 is ignored. table 1 burst definition burst starting column order of accesses within a burst length address type = sequential type = interleaved a0 2 0 0-1 0-1 1 1-0 1-0 a1 a0 0 0 0-1-2-3 0-1-2-3 4 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0 a2 a1 a0 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 8 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 full n = a0-a8 cn, cn + 1, cn + 2 page cn + 3, cn + 4... not supported (512) (location 0-511) cn - 1, cn m2 0 0 0 0 1 1 1 1 m1 0 0 1 1 0 0 1 1 m0 0 1 0 1 0 1 0 1 m3 = 0 1 2 4 8 reserved reserved reserved full page m3 = 1 1 2 4 8 reserved reserved reserved reserved operating mode standard operation all other states reserved 0 - 0 - defined - 0 1 burst type sequential interleaved cas latency reserved 1 2 3 reserved reserved reserved reserved m6 0 0 0 0 1 1 1 1 m4 0 1 0 1 0 1 0 1 m5 0 0 1 1 0 0 1 1 burst length burst length cas latency bt a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 mode register (mx) address bus 9 7 654 3 8 2 1 0 m3 m6-m0 m8 m7 op mode a10 ba 10 11 reserved* wb 0 1 write burst mode programmed burst length single location access m9 *should program m11, m10 = 0, 0 to ensure compatibility with future devices. figure 1 mode register definition
2, 4 meg x 64 sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm02.p65 C rev. 6/98 ? 1998, micron technology, inc. 12 2, 4 meg x 64 sdram dimms obsolete absolute maximum ratings* voltage on v dd supply relative to v ss .......... -1v to +4.6v voltage on inputs, nc or i/o pins relative to v ss ................................................ -1v to +4.6v operating temperature, t a (ambient) .......... 0 c to +70 c storage temperature (plastic) .................... -55 c to +125 c power dissipation ............................................................. 8w *stresses greater than those listed under absolute maxi- mum ratings may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those indi- cated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. dc electrical characteristics and operating conditions (notes: 1, 6) (v dd = +3.3v 0.3v) parameter/condition symbol min max units notes supply voltage v dd 3 3.6 v input high voltage: logic 1; all inputs v ih 2v dd + 0.3 v 25 input low voltage: logic 0; all inputs v il -0.5 0.8 v 25 input leakage current: dqmb0-dqmb7 i i 1 -10 10 m a22 any input 0v v in v dd ck0-ck3, s0#-s3# i i 2 -20 20 m a (all other pins not under test = 0v) cke0-cke1 i i 3 -40 40 m a ras#, cas#, a0-a10, ba0, we# i i 4 -80 80 m a22 output leakage current: dq0-dq63 i oz -10 10 m a22 dqs are disabled; 0v v out v dd output levels: v oh 2.4 C v output high voltage (i out = -2ma) output low voltage (i out = 2ma) v ol C 0.4 v icc specifications and conditions (notes: 1, 6, 11, 13) (v dd = +3.3v 0.3v) parameter/condition symbol size -10b -662 units notes operating current: active mode; 16mb 840 720 burst = 2; read or write; t rc = t rc (min) ; i cc 1 ma 3, 18, cas latency = 3; t ck = 15ns 32mb 1,200 1,040 19 standby current: power-down mode; i cc 2 16mb 24 16 ma t ck = 15ns (10ns for -10b); cke v il (max); all banks idle 32mb 48 32 standby current: active mode; s0#-s3# = high; 16mb 360 320 t ck = 15ns (10ns for -10b); cke = high; all banks i cc 3 ma 3, 12, active after t rcd met; no accesses in progress 32mb 720 640 19 operating current: burst mode; continuous burst; 16mb 1,000 680 read or write; t ck = 15ns (10ns for -10b); all banks active; i cc 4 ma 3, 18, cas latency = 3 32mb 1,360 1,000 19 auto refresh current: t rc = t rc (min); cas latency = 3; i cc 5 16mb 760 680 ma 3, 12, cke = high; s0#-s3# = high; t ck = 15ns (10ns for -10b) 32mb 1,120 1,000 18, 19 self refresh current: i cc 6 16mb 8 16 ma 4 cke 0.2v 32mb 16 32 max
2, 4 meg x 64 sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm02.p65 C rev. 6/98 ? 1998, micron technology, inc. 13 2, 4 meg x 64 sdram dimms obsolete sdram component* ac electrical characteristics (notes: 5, 6, 7, 8, 9, 11) ac characteristics -10b -662 parameter symbol min max min max units notes cl = 3 t ac 6 7.5 ns access time from clk (positive edge) cl = 2 t ac 9 9 ns cl = 1 t ac 27 27 ns address hold time t ah 1 1 ns address setup time t as 2 3 ns clk high-level width t ch 3 3.5 ns clk low-level width t cl 3 3.5 ns cl = 3 t ck 8 10 ns 26 clock cycle time cl = 2 t ck 12 15 ns 26 cl = 1 t ck 30 30 ns 26 cke hold time t ckh 1 1 ns cke setup time t cks 2 3 ns cs#, ras#, cas#, we#, dqm hold time t cmh 1 1 ns cs#, ras#, cas#, we#, dqm setup time t cms 2 3 ns data-in hold time t dh 1 1 ns data-in setup time t ds 2 3 ns cl = 3 t hz 6 8 ns 10 data-out high-impedance time cl = 2 t hz 7 10 ns 10 cl = 1 t hz 15 15 ns 10 data-out low-impedance time t lz 1 2 ns data-out hold time t oh 3 3 ns active to precharge command period t ras 50 120,000 60 120,000 ns auto refresh, active command period t rc 80 90 ns active to read or write delay t rcd 20 30 ns refresh period (4,096 cycles) t ref 64 64 ms precharge command period t rp 24 30 ns 21 active bank a to active bank b command period t rrd 20 20 ns transition time t t 0.3 1.2 1 1.2 ns 7 write recovery time t wr 1 1 t ck 27 10 10 ns 28 exit self refresh to active command t xsr 80 90 ns 20 capacitance 16mb 32mb parameter symbol min max min max units notes input capacitance: a0-a10, ba0, ras#, cas#, we# c i 1 25 45 45 88 pf 2 input capacitance: s0#-s3#, ck0-ck3 c i 2 15 25 15 25 pf 2 input capacitance: cke0, cke1 c i 3 25 45 25 45 pf 2 input capacitance: dqmb0#-dqmb7# c i 4 48714pf2 input capacitance: scl, sa0-sa2 c i 5 C6C6pf2 input/output capacitance: dq0-dq63, sda c io 6 101215pf 2 *specifications for the sdram components used on the module.
2, 4 meg x 64 sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm02.p65 C rev. 6/98 ? 1998, micron technology, inc. 14 2, 4 meg x 64 sdram dimms obsolete ac functional characteristics (notes: 5, 6, 7, 8, 9, 11) parameter symbol -10b -662 units notes read/write command to read/write command t ccd 1 1 t ck 17 cke to clock disable or power-down entry mode t cked 1 1 t ck 14 cke to clock enable or power-down exit setup mode t ped 1 1 t ck 14 dqm to input data delay t dqd 0 0 t ck 17 dqm to data mask during writes t dqm 0 0 t ck 17 dqm to data high-impedance during reads t dqz 2 2 t ck 17 write command to input data delay t dwd 0 0 t ck 17 data-in to active command t dal 4 3 t ck 15, 21 data-in to precharge command t dpl 1 1 t ck 16, 24 last data-in to precharge command t rdl 1 1 t ck 16 last data-in to burst stop command t bdl 1 1 t ck 17, 24 last data-in to new read/write command t cdl 1 1 t ck 17 load mode register command to active or refresh command t mrd 2 2 t ck 29 data-out to high-impedance from precharge command cl = 3 t roh 3 3 t ck 17 cl = 2 t roh 2 2 t ck 17 cl = 1 t roh 1 1 t ck 17 sdram component* electrical timing characteristics between -8 speed options (notes: 5, 6, 8, 9, 11) ac characteristics -8e -8d -8c -8b -8a parameter symbol min max min max min max min max min max units notes access time from clk (pos. edge) cl = 3 t ac 66666ns30 cl = 2 t ac 67999ns30 cl = 1 t ac 27 27 27 27 27 ns 30 clock cycle time cl = 3 t ck88888 ns30 cl = 2 t ck 10 10 12 12 12 ns 30 cl = 1 t ck 30 30 30 30 30 ns 30 active to read or write delay t rcd 20 20 20 20 24 ns 30 precharge command period t rp 20 20 20 24 24 ns 30 auto refresh, active command period t rc 70 70 70 80 80 ns 30 write recovery time t wr22222 t ck 21 100 mhz speed reference (cl- t rcd- t rp) 2-2-2 2-2-2 3-2-2 3-2-3 3-3-3 clks *specifications for the sdram components used on the module.
2, 4 meg x 64 sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm02.p65 C rev. 6/98 ? 1998, micron technology, inc. 15 2, 4 meg x 64 sdram dimms obsolete serial presence-detect eeprom dc operating conditions (notes: 1) (v dd = +3.3v 0.3v) parameter/condition symbol min max units notes supply voltage v dd 3 3.6 v input high voltage: logic 1; all inputs v ih v dd 0.7 v dd + 0.5 v input low voltage: logic 0; all inputs v il -1 v dd 0.3 v output low voltage: i out = 3ma v ol C 0.4 v input leakage current: v in = gnd to v dd i li C10 m a output leakage current: v out = gnd to v dd i lo C10 m a standby current: i sb C30 m a scl = sda = v dd - 0.3v; all other inputs = gnd or 3.3v +10% power supply current: i cc C2ma scl clock frequency = 100 khz serial presence-detect eeprom ac operating conditions (notes: 1) (v dd = +3.3v 0.3v) parameter/condition symbol min max units notes scl low to sda data-out valid t aa 0.3 3.5 m s time the bus must be free before a new transition can start t buf 4.7 m s data-out hold time t dh 300 ns sda and scl fall time t f 300 ns data-in hold time t hd:dat 0 m s start condition hold time t hd:sta 4 m s clock high period t high 4 m s noise suppression time constant at scl, sda inputs t i 100 ns clock low period t low 4.7 m s sda and scl rise time t r1 m s scl clock frequency t scl 100 khz data-in setup time t su:dat 250 ns start condition setup time t su:sta 4.7 m s stop condition setup time t su:sto 4.7 m s write cycle time t wrc 10 ms 23
2, 4 meg x 64 sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm02.p65 C rev. 6/98 ? 1998, micron technology, inc. 16 2, 4 meg x 64 sdram dimms obsolete notes 1. all voltages referenced to v ss . 2. this parameter is sampled. v dd = +3.3v; f = 1 mhz. 3. i cc is dependent on output loading and cycle rates. specified values are obtained with minimum cycle time and the outputs open. 4. enables on-chip refresh and address counters. 5. the minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (0 c t a 70 c) is ensured. 6. an initial pause of 100 m s is required after power-up, followed by two auto refresh commands, before proper device operation is ensured. the two auto refresh command wake-ups should be repeated any time the t ref refresh requirement is exceeded. 7. ac characteristics assume t t = 1ns. 8. in addition to meeting the transition rate specifica- tion, the clock and cke must transit between v ih and v il (or between v il and v ih ) in a monotonic manner. 9. outputs measured at 1.5v with equivalent load: 15. timing actually specified by t wr plus t rp; clock(s) specified as a reference only at minimum cycle rate. 16. timing actually specified by t wr. 17. required clocks are specified by jedec functionality and are not dependent on any timing parameter. 18. the i cc current will decrease as the cas latency is reduced. this is because the maximum cycle rate is slower as the cas latency is reduced. 19. address transitions an average of one transition every 30ns (20ns on -10b). 20. clk must be toggled a minimum of two times during this period. 21. based on t ck = 100 mhz for -10b and 66 mhz for -662. 22. 16mb module values will be half of those shown. 23. the spd eeprom write cycle time ( t wrc) is the time from a valid stop condition of a write sequence to the end of the eeprom internal erase/program cycle. during the write cycle, the eeprom bus interface circuit is disabled, sda remains high due to the pull-up resistor, and the eeprom does not respond to its slave address. 24. it is recommended that the dram controller use two clocks for t wr to support future design requirements. 25. v ih overshoot: v ih (max) = v dd + 2v for a pulse width 10ns, and the pulse width cannot be greater than one third of the cycle rate. v il undershoot: v il (min) = -2v for a pulse width 10ns, and the pulse width cannot be greater than one third of the cycle rate. 26. 16mb module values will be half of those shown. 27. auto precharge mode only. 28. precharge mode only. 29. jedec and pc100 specify three clocks. 30. these five parameters vary between speed grades and define the differences between the -8 sdram speeds: -8a, -8b, -8c, -8d and -8e. all other -8 timing parameters remain constant. q 50pf 10. t hz defines the time at which the output achieves the open circuit condition; it is not a reference to v oh or v ol . the last valid data element will meet t oh before going high-z. 11. ac timing tests have v il = 0v and v ih = 3v, with timing referenced to 1.5v crossover point. 12. other input signals are allowed to transition no more than once in any 30ns period (20ns on -10b) and are otherwise at valid v ih or v il levels. 13. i cc specifications are tested after the device is properly initialized. 14. timing actually specified by t cks; clock(s) specified as a reference only at minimum cycle rate.
2, 4 meg x 64 sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm02.p65 C rev. 6/98 ? 1998, micron technology, inc. 17 2, 4 meg x 64 sdram dimms obsolete serial presence-detect eeprom timing parameters symbol min max units t aa 0.3 3.5 m s t buf 4.7 m s t dh 300 ns t f 300 ns t hd:dat 0 m s t hd:sta 4 m s spd eeprom symbol min max units t high 4 m s t low 4.7 m s t r1 m s t su:dat 250 ns t su:sta 4.7 m s t su:sto 4.7 m s scl sda in sda out t low t su:sta t hd:sta t f t high t r t buf t dh t aa t su:sto t su:dat t hd:dat undefined
2, 4 meg x 64 sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm02.p65 C rev. 6/98 ? 1998, micron technology, inc. 18 2, 4 meg x 64 sdram dimms obsolete note: 1. all dimensions in inches (millimeters) max or typical where noted. min 168-pin dimm df-17 (16mb, 66 mhz) .125 (3.18) max .054 (1.37) .046 (1.17) pin 1 (pin 85 on backside) .700 (17.78) typ .118 (3.00) (2x) .118 (3.00) typ 4.550 (115.57) .050 (1.27) typ .118 (3.00) typ .039 (1.00) typ .079 (2.00) r (2x) .039 (1.00)r (2x) front view .128 (3.25) .118 (3.00) pin 84 (pin 168 on backside) (2x) 1.155 (29.34) 1.145 (29.08) .250 (6.35) typ 1.661 (42.18) 2.625 (66.68) 5.256 (133.50) 5.244 (133.20) 168-pin dimm df-29 (16mb, 100 mhz) .054 (1.37) .046 (1.17) pin 1 (pin 85 on backside) .700 (17.78) typ .118 (3.00) (2x) .118 (3.00) typ .250 (6.35) typ 4.550 (115.57) .050 (1.27) typ .118 (3.00) typ .039 (1.00) typ .079 (2.00) r (2x) .039 (1.00)r (2x) front view .128 (3.25) .118 (3.00) pin 84 (pin 168 on backside) (2x) 1.255 (31.88) 1.245 (31.62) .125 (3.18) max 5.256 (133.50) 5.244 (133.20)
2, 4 meg x 64 sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm02.p65 C rev. 6/98 ? 1998, micron technology, inc. 19 2, 4 meg x 64 sdram dimms obsolete note: 1. all dimensions in inches (millimeters) max or typical where noted. min note: 1. all dimensions in inches (millimeters) max or typical where noted. min 168-pin dimm df-28 (32mb, 100 mhz) .054 (1.37) .046 (1.17) pin 1 (pin 85 on backside) .700 (17.78) typ .118 (3.00) (2x) .118 (3.00) typ .250 (6.35) typ 4.550 (115.57) .050 (1.27) typ .118 (3.00) typ .039 (1.00) typ .079 (2.00) r (2x) .039 (1.00)r (2x) front view .128 (3.25) .118 (3.00) pin 84 (pin 168 on backside) (2x) 1.255 (31.88) 1.245 (31.62) .157 (4.00) max 5.256 (133.50) 5.244 (133.20) .157 (4.00) max .054 (1.37) .046 (1.17) pin 1 (pin 85 on backside) .700 (17.78) typ .118 (3.00) (2x) .118 (3.00) typ 4.550 (115.57) .050 (1.27) typ .118 (3.00) typ .039 (1.00) typ .079 (2.00) r (2x) .039 (1.00)r (2x) front view .128 (3.25) .118 (3.00) pin 84 (pin 168 on backside) (2x) .250 (6.35) typ 1.661 (42.18) 2.625 (66.68) 1.155 (29.34) 1.145 (29.08) 5.256 (133.50) 5.244 (133.20) 168-pin dimm df-18 (32mb, 66 mhz)

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